SMID processing unit performing concurrent load/store and ALU operations
US11640302B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | May 21, 2019 |
| Grant date | May 2, 2023 |
| Priority date | — |
| Expiry date | Oct 2, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8015
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device comprising: a plurality of ALUs; a set of registers; a memory; a memory interface between the registers and the memory; a control unit controlling the ALUs by generating: at least one cycle i including both implementing at least one first computing operation by way of an arithmetic logic unit and downloading a first dataset from the memory to at least one register; at least one cycle ii, following the at least one cycle i, including implementing a second computing operation by way of an arithmetic logic unit, for which second computing operation at least part of the first dataset forms at least one operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.