Processing pipeline where fast data passes slow data
US11640360B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2022 |
| Grant date | May 2, 2023 |
| Priority date | — |
| Expiry date | Jan 25, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments relate to an inline encryption engine in a memory controller configured to process data read from a memory, including: a first data pipeline configured to receive data that is plaintext data and a first validity flag; a second data pipeline having the same length as the first data pipeline configured to: receive data that is encrypted data and a second validity flag; decrypt the encrypted data from the memory and output decrypted plaintext data; an output multiplexer configured to select and output data from either the first pipeline or the second pipeline; and control logic configured to control the output multiplexer, wherein the control logic is configured to output valid data from the first pipeline when the second pipeline does not have valid output decrypted plaintext data available.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.