Address decoder for a multi-chip system
US11640366B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2021 |
| Grant date | May 2, 2023 |
| Priority date | — |
| Expiry date | Dec 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7807
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address decoder for a source node in a multi-chip system is disclosed, which can perform parallel decoding steps to determine whether a transaction from the source node is addressed to a target node in a local integrated circuit (IC) or a remote IC, and whether the source node is allowed to access that target node. Based on the outcome of both the decoding steps, the transaction can be either blocked by the address decoder, or routed to the target node. If the transaction is addressed to the remote IC, but the source node is not allowed to access the target node on the remote IC, the transaction can be terminated by the address decoder in the local IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.