Apparatus and methods for high-speed drivers
US11640367B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 12, 2021 |
| Grant date | May 2, 2023 |
| Priority date | — |
| Expiry date | Oct 12, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods for high-speed drivers are provided herein. In certain embodiments, a high-speed driver multiplexes two or more data streams. The high-speed driver is implemented with a mux-then-driver topology that provides multiplexing in a predriver circuit. Thus, the multiplexer is eliminated from the full rate output path to relax timing. Driver amplitude control schemes are also disclosed in which a controllable driver includes a group of differential series source transistor (SST) driver slices that are connected in parallel with one another to drive a pair of output terminals, and a group of attenuator slices that are connected in parallel with one another across the pair of output terminals. Additionally, the controllable driver includes a control circuit that activates an attenuator slice for each SST driver slice that is decommissioned to provide output amplitude control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.