Internal node jumper for memory bit cells
US11640939B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2021 |
| Grant date | May 2, 2023 |
| Priority date | — |
| Expiry date | Nov 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.