High-speed switch with accelerated switching time
US11641196B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 2022 |
| Grant date | May 2, 2023 |
| Priority date | — |
| Expiry date | Feb 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/693
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.