C-PHY half-rate wire state encoder and decoder
US11641294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2022 |
| Grant date | May 2, 2023 |
| Priority date | — |
| Expiry date | Jan 31, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/493
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus, and systems provide improved throughput on a communication link. An apparatus has a plurality of line drivers, a first wire state encoder configured to receive a first symbol in a sequence of symbols when a 3-wire link is in a first signaling state, and to define a second signaling state for the 3-wire link based on the first symbol and the first signaling state, a second wire state encoder configured to receive a second symbol in the sequence of symbols, and to define a third signaling state for the 3-wire link based on the second symbol and the second signaling state. The first symbol immediately precedes the second symbol in the sequence of symbols. The 3-wire link transitions from the first to the second signaling state, and from the second to the third signaling state in consecutive transmission intervals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.