Systems and methods for memory layout determination and conflict resolution
US11645057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2020 |
| Grant date | May 9, 2023 |
| Priority date | — |
| Expiry date | Mar 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dataflow graph has operation units that are configured to be producer operation units to produce tensors for execution of the application, and to be consumer operation units to consume the tensors for execution of the application. Compile time logic is configured to process the dataflow graph to determine, for the tensors, expected producer memory layouts, expected consumer memory layouts, and current memory layouts. The expected producer memory layouts specify memory layouts required by the producer operation units that produce the tensors. The expected consumer memory layouts specify the memory layouts required by the consumer operation units that consume the tensors. The current memory layouts specify the memory layouts of the tensors. Each of the memory layouts includes a vector dimension and at least one of a vector ordering and a data alignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.