Error detection within an integrated circuit chip
US11645143B2 · kind B2 · utility
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3References
22Claims
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Inventor
Key dates
| Filing date | Jul 31, 2019 |
| Grant date | May 9, 2023 |
| Priority date | — |
| Expiry date | Jul 31, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing error detection within an integrated circuit chip analyses transactions communicated over interconnect circuitry of the integrated circuit chip to detect whether a message contains a data error. A memory of the integrated circuit chip coupled to the interconnect circuitry is scanned to detect whether there is a data error stored in the memory, and in response to detecting a data error in a transaction communicated over the interconnect circuitry and/or a data error stored in the memory, a dedicated action indicative of a data error is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.