Method of fabricating array substrate, array substrate and display device
US11646327B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2021 |
| Grant date | May 9, 2023 |
| Priority date | — |
| Expiry date | Oct 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1216
Abstract
A display device is disclosed. The display device includes a display area and a wiring area. The display area is disposed with a first thin film transistor which is an oxide thin film transistor and a second thin film transistor which is a low temperature poly-silicon thin film transistor. A distance between a first active layer of the first thin film transistor and a substrate is different from a distance between a second active layer of the second thin film transistor and the substrate. The first thin film transistor includes first vias that receive a first source/drain. The second thin film transistor includes second vias that receives a second source/drain. The wiring area is provided with a groove. The groove includes a first sub-groove and a second sub-groove that are stacked, and depths of the second vias are substantially equal to a depth of the second sub-groove.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.