Securely booting a processor complex via a securely bootable subsystem
US11650741B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 2020 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | Sep 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques in electronic systems, such as in systems including a processor complex having one or more system processors and one or more memories, provide improvements in one or more of system security, performance, cost, and efficiency. In some embodiments, the system includes secure boot logic (SBL) having immutable hardware enabled, in response to a reset of the system, to securely boot one or more boot processors of the SBL to execute known-good executable code. The SBL is then enabled to securely boot the one or more system processors to execute system code stored in a non-volatile one of the memories by copying the system code to another one of the memories from which at least one of the system processors is able to access the system code for a respective initial instruction fetch. The non-volatile memory is not accessible to the system processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.