Patent · US Active

Reconfigurable memory mapped peripheral registers

US11650930B2 · kind B2 · utility

0Cited by
3References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 23, 2021
Grant dateMay 16, 2023
Priority date
Expiry dateSep 23, 2041

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2212/7201
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A computing device, including a processor; a memory, wherein the memory is accessible for memory operations via a range of logical memory addresses; a peripheral interface including a first control register; and a peripheral address remapping module configured to determine that the peripheral interface is unused for interfacing with a peripheral; determine a first memory address for accessing the first control register; determine a first logical memory address, the first logical memory address outside of the range of logical memory addresses for accessing the memory; and map the first logical memory address to the first memory address, wherein the first control register is accessible for memory operations using the first logical memory address.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.