Processor authentication method
US11651064B2 · kind B2 · utility
2Cited by
8References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Mar 27, 2020 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | Jul 1, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and at least one previously-executed opcode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.