Ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial FFT
US11651766B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2021 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | May 24, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG10L25/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses an ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial fast Fourier transform (FFT), and belongs to the technical field of computation, calculation or counting. The circuit is oriented to the field of intelligence, and is integrally composed of a pre-process module, a windowing module, a Fourier transform module, a Mel filtering module, an adjacent frame merging module, a discrete cosine transform (DCT) module and other modules by optimizing the architecture of a Mel-frequency Cepstral Coefficients (MFCC) algorithm. Large-scale storage caused by framing is avoided in a non-overlapping framing mode, storage contained in the MFCC algorithm is further reduced, and the circuit area and the power consumption are greatly reduced. An FFT algorithm in the feature extraction circuit adopts a serial pipeline mode to process data, makes full use of the characteristics of serial inflow of audio data, and further reduces the storage area and operations of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.