Adaptive program verify scheme for performance improvement
US11651821B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2021 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | Oct 18, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/349
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device includes a controller coupled to one or more memory devices. The controller is configured to determine one or more first wordlines within the memory device that needs more than one pulse for programming and one or more second wordlines within the memory device that needs one pulse and no program verify. The locations of the one or more first wordlines and the one or more second wordlines are stored in a data structure of the memory device. During program operations, the controller utilizes the data structure to determine whether the one or more wordlines being programmed requires only one pulse and no program verify or a multi-loop program. The data structure is updated after an EPWR and/or XOR parity operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.