Layered super-reticle computing : architectures and methods

US11656662B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Simon C. Steely, Jr. · Hudson, US
• Richard J. Dischler · Bolton, US
• David Bach · Boulder, US
• Olivier Franza · Brookline, US
• William J. Butera · Ditzingen, DE
• Christian Karl · Gaming, AT
• Benjamin Keen · Marlborough, US
• Brian Leung · Bellevue, US

Key dates

• Filing date: Feb 11, 2021
• Grant date: May 23, 2023
• Expiry date: Jun 14, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2225/06541
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.