Asymmetrical processor memory architecture
US11656874B2 · kind B2 · utility
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3References
17Claims
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Key dates
| Filing date | Oct 8, 2015 |
| Grant date | May 23, 2023 |
| Priority date | — |
| Expiry date | Dec 4, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asymmetrical processing system is provided. The processor has a vector unit comprised of one or more computational units coupled with a vector memory space and a scalar unit coupled with a data memory space and the vector memory space, the scalar unit accessing one or more memory locations within the vector memory space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.