Apparatus and method
US11657003B2 · kind B2 · utility
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2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2020 |
| Grant date | May 23, 2023 |
| Priority date | — |
| Expiry date | Jun 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus comprises two or more processing devices each having an associated translation lookaside buffer to store translation data defining address translations between virtual and physical memory addresses, each address translation being associated with a respective virtual address space; and control circuitry to control the transfer of at least a subset of the translation data from the translation lookaside buffer associated with a first processing device to the translation lookaside buffer associated with a second, different, processing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.