Avalon-to-Axi4 bus conversion method
US11657011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2020 |
| Grant date | May 23, 2023 |
| Priority date | — |
| Expiry date | Dec 9, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an Avalon-to-Axi4 bus conversion method, including: in case that an Avalon bus is an Avalon_st bus, receiving Avalon_st bus data, performing a logical process on the received Avalon_st bus data, and then outputting corresponding Axi4_st bus data; and in case that the Avalon bus is an Avalon_mm bus, receiving a signal transmitted by each channel of the Avalon_mm bus, framing and storing the signal in asynchronous First Input First Output (FIFO), and in case that a device corresponding to an Axi4 bus is ready, reading the signal from the asynchronous FIFO, and outputting the signal to a corresponding channel of the Axi4 bus according to a timing relationship of the Axi4 bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.