Aware variable fill pattern generator
US11657202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2020 |
| Grant date | May 23, 2023 |
| Priority date | — |
| Expiry date | Dec 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53228
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A layout file for an integrated circuit has drawn geometries. Variable fill geometries are added to local areas based on densities of the drawn geometries in windows associated with the local areas and on the global density of all the drawn geometries in the layout file. Each window has a separate local area associated with it. The densities of the variable fill geometries in the local areas are not all equal. Densities of the fill geometries are higher in local areas associated with windows having lower densities of the drawn geometries, and for lower values of the global density. The layout file is stored in a computer-readable medium which may be used to produce a photomask for manufacturing an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.