Trench-gate power MOSFET with optimized layout

US11658237B2 · kind B2 · utility

Assignee

• ZJU-HANGZHOU GLOBAL SCIENTIFIC AND TECHNOLOGICAL INNOVATION CENTER · CN

Inventors

• NA REN · Los Angeles, US
• Kuang SHENG · Zhejiang, CN
• Zhengyun ZHU · Zhejiang, CN
• Hu Chen · Beijing, CN

Key dates

• Filing date: Sep 13, 2022
• Grant date: May 23, 2023
• Expiry date: Sep 13, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/108

Abstract

A trench-gate power MOSFET with optimized layout, comprising: a substrate; a first semiconductor region formed on the substrate, having a first doping type; mutually separated trench isolation gate structure, formed on the first semiconductor region, the trench isolation gate structure includes an gate oxide layer and a gate electrode; a second semiconductor region and a third semiconductor region formed between any two adjacent structures of mutually separated trench isolation gate structures; and a first shielding region, formed under each of the third semiconductor regions, connecting simultaneously with multiple mutually separated trench isolation structures.