Source and drain enabled conduction triggers and immunity tolerance for integrated circuits
US11658481B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 14, 2022 |
| Grant date | May 23, 2023 |
| Priority date | — |
| Expiry date | Jan 14, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Integrated circuits with enhanced EOS/ESD robustness and methods of designing same. One such integrated circuit includes a plurality of input/output pads, a positive voltage rail, a ground voltage rail, a collection of internal circuits representing the operational core of the integrated circuit, a plurality of input/output buffering circuits connected as inputs and outputs to the internal circuits, wherein the internal circuits and the input/output buffering circuits comprise functional devices, and a plurality of EOS/ESD protection circuits interconnected with the input/output pads to limit ESD voltage and/or shunt ESD current away from the functional devices. At least one of the EOS/ESD protection circuits is a MOSFET. The MOSFET has a source region having an accompanying ohmic contact. The MOSFET further has a rectifying junction contact in place of a drain region and accompanying ohmic contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.