Adjustable delay line devices and methods thereof
US11658647B2 · kind B2 · utility
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3References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2021 |
| Grant date | May 23, 2023 |
| Priority date | — |
| Expiry date | Aug 17, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switched delay section for an integrated circuit device is disclosed. The switched delay section includes a segmented inductor loop comprising a plurality of segments separated by nodes. A plurality of capacitors are coupled between the segmented inductor loop to provide a plurality of delay sections. An image loop is in electrical communication with the segmented inductor loop. The image loop includes a switch configured to place the plurality of capacitors in one of a high capacitance or a low capacitance state to provide a variable delay value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.