System for providing a low latency and fast switched cascaded dual phased lock loop (PLL) architecture for die-to-die / system-on-chip (SoC) interfaces
US11662765B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2022 |
| Grant date | May 30, 2023 |
| Priority date | — |
| Expiry date | Jan 31, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for providing low latency frequency switching includes operating a first processing component on a first die and operating a second processing component on a second die with the same first clock signal having a first frequency. A request to switch the first frequency to a second, new frequency is received and a second clock signal having the second, new frequency is produced. Data flow between the first die and second die may be stopped. And then the second clock signal is transmitted to a dual phased locked loop architecture on a die interface. A PCLK signal is created from the combined first and second clock signals and an NCLK signal is created from the second clock signal. Next, the PCLK signal is divided and aligned with the NCLK signal. Once the PCLK signal is aligned with the NCLK signal, data flow is resumed between the two dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.