Supporting large-word operations in a reduced instruction set computer (“RISC”) processor
US11663009B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2021 |
| Grant date | May 30, 2023 |
| Priority date | — |
| Expiry date | Oct 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Reduced Instruction Set Computer (“RISC”) supporting large-word operations in a computing environment is disclosed. In one implementation, in response to receiving one or more control signals from a central processing unit (“CPU”), a set of operations are executed on a state of a special purpose execution unit (“SPU”) having a plurality of SPU registers, the SPU being associated with the CPU and the state of the SPU having word widths of one or more of the plurality of registers being greater in size than word widths of a plurality of CPU registers of a computing system and a set of state-master bits to synchronize the state of the SPU and a state of the CPU. The results of the set of operations are stored in the plurality of CPU registers or an alternative set of the plurality of SPU registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.