Techniques for configuring a processor to function as multiple, separate processors

US11663036B2 · kind B2 · utility

Assignee

• NVIDIA Corporation · US

Inventors

• Jerome F. Duluk, Jr. · Palo Alto, US
• Gregory Scott Palmer · Cedar Park, US
• Jonathon Stuart Ramsey Evans · Santa Clara, US
• Shailendra Singh · Thane, IN
• Samuel H. Duncan · Arlington, US
• Wishwesh Anil Gandhi · Sunnyvale, US
• Lacky V. Shah · Los Altos, US
• Eric Rock · San Jose, US
• Feiqi Su · Cupertino, US
• James Leroy Deming · Madison, US
• Alan Menezes · San Jose, US
• Pranav Vaidya · San Jose, US
• Praveen Joginipally · San Jose, US
• Timothy John Purcell · Provo, US
• Manas Mandal · Palo Alto, US

Key dates

• Filing date: Sep 5, 2019
• Grant date: May 30, 2023
• Expiry date: Oct 4, 2039

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T1/20
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.