System-on-chip performing address translation and operating method thereof
US11663131B2 · kind B2 · utility
1Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2021 |
| Grant date | May 30, 2023 |
| Priority date | — |
| Expiry date | Jul 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method of a system-on-chip includes outputting a prefetch command in response to an update of mapping information on a first read target address, the update occurring in a first translation lookaside buffer storing first mapping information of a second address with respect to a first address, and storing, in response to the prefetch command, in a second translation lookaside buffer, second mapping information of a third address with respect to at least some second addresses of an address block including a second read target address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.