Neural network processor for compressing featuremap data and computing system including the same
US11664818B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 6, 2020 |
| Grant date | May 30, 2023 |
| Priority date | — |
| Expiry date | Sep 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a neural network device including at least one processor configured to implement an arithmetic circuit configured to generate third data including a plurality of pixels based on a neural network configured to perform an arithmetic operation on first data and second data, and a compressor configured to generate compressed data by compressing the third data, wherein the compressor is further configured to generate, as the compressed data, bitmap data comprising location information about a non-zero pixel having a non-zero data value among the plurality of pixels based on a quad-tree structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.