Semiconductor memory device having spacer capping pattern disposed between burried dielectic pattern and an air gap and method of fabricating same
US11665883B2 · kind B2 · utility
6Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Mar 16, 2021 |
| Grant date | May 30, 2023 |
| Priority date | — |
| Expiry date | May 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/4821
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.