Method and structure for CMOS-MEMS thin film encapsulation
US11667517B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2020 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Aug 14, 2040 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2203/0735
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.