Patent · US Active

Addressable test chip

US11668748B2 · kind B2 · utility

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14Claims

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Assignee

SEMITRONIX CORPORATION

Inventors

Fan Lan · Shanghai, CN
Weiwei Pan · Taiyuan, CN
Shenzhi Yang · Yorktown Heights, US
Yongjun Zheng · Fuzhou, CN

Key dates

Filing date	Jan 25, 2022
Grant date	Jun 6, 2023
Priority date	—
Expiry date	Jan 25, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/2886
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A test apparatus for testing electrical parameters of a target chip includes: a function generator; a switch matrix module; a plurality of source measurement units (SMUs); at least one of the SMUs is configured to provide power supply for the target chip; at least one of the SMUs is coupled to the switch matrix module; and at least two of said SMUs are test SMUs coupled to ports of the target chip and the function generator.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.