Clock generation circuit
US11669125B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 2022 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Jun 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The clock generation circuit outputs a clock signal with a constant cycle by repeating the following operations: when an enable signal becomes a H level, the clock signal immediately rises, and a sense end is changed to a L level via a first capacitor, then a voltage of the sense end is gradually increased via a resistor, and when the sense end reaches a predetermined potential, an output of a second inverter becomes the L level, the clock signal becomes the L level, an inverted clock signal becomes the H level, and accordingly the sense end becomes the H level; and thereafter, a current flows via the resistor so that the voltage of the sense end decreases gradually, when the sense end reaches a predetermined potential, the output of the second inverter becomes a H level, the clock signal becomes the H level, the sense end is changed to a L level via the first capacitor, then the voltage of the sense end is gradually increased via the resistor, and when the sense end reaches a predetermined potential, the output of the second inverter becomes the L level and the clock signal becomes the L level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.