Hybrid directory and snoopy-based coherency to reduce directory update overhead in two-level memory
US11669454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2019 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | May 21, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes one or more cores having cache, a cache home agent (CHA), a near memory controller, to near memory, and a far memory controller, which is to: receive a first memory read operation from the CHA directed at a memory address; detect a miss for the first memory address at the near memory; issue a second memory read operation to the far memory controller to retrieve a cache line, having first data, from the memory address of far memory; receive the cache line from the far memory controller in response to the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote sockets to maintain data coherence for the cache line in an absence of directory state in the far memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.