Hardware architecture for accelerating artificial intelligent processor
US11669715B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 30, 2019 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Feb 23, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware architecture that may include: a host, a frontal engine, a parietal engine, a renderer engine, an occipital engine, a temporal engine, and a memory. The frontal engine may obtain a 5D tensor from the host and divide it into several groups of tensors. These groups of tensors may be sent or transmitted to the parietal engine, and the parietal engine may take the groups of tensors to further divide them into several tensors. The parietal engine may send these tensors to the renderer engine for execution and may send a partial amount of tensors to the occipital engine. The occipital engine may accumulate the partial amount of tensors and may execute them. The occipital engine may send the output feature as the final tensor to the temporal engine. The temporal engine may compress the final tensor before storing or saving it to the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.