Display and a multi-level voltage generator thereof
US11670211B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2022 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Aug 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/028
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multi-level voltage generator includes P-type metal-oxide-semiconductor (PMOS) transistors that generate corresponding positive voltages and a common voltage respectively, each PMOS transistor having a source connected to corresponding generated voltage, and a drain connected to an output node to provide the corresponding generated voltage; N-type metal-oxide-semiconductor (NMOS) transistors that generate corresponding negative voltages and the common voltage respectively, each NMOS transistor having a source connected to corresponding generated voltage, and a drain connected to the output node to provide the corresponding generated voltage; and body-voltage selectors that adaptively select a body voltage for the plurality of PMOS transistors and NMOS transistors respectively, except PMOS transistor associated with a highest positive voltage and NMOS transistor associated with a lowest negative voltage with body and source connected together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.