Accelerator controlling memory device, computing system including accelerator, and operating method of accelerator
US11670355B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2021 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Aug 20, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.