Artificial reality system with reduced SRAM power leakage
US11670364B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2021 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Jul 31, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System on a Chip (SoC) integrated circuits are configured to reduce Static Random-Access Memory (SRAM) power leakage. For example, SoCs configured to reduce SRAM power leakage may form part of an artificial reality system including at least one head mounted display. Power switching logic on the SoC includes a first power gating transistor that supplies a first, higher voltage to an SRAM array when the SRAM array is in an active state, and a third power gating transistor that isolates a second power gating transistor from the first, higher voltage when the SRAM array is in the active state. The second power gating transistor further supplies a second, lower voltage to the SRAM array when the SRAM array is in a deep retention state, such that SRAM power leakage is reduced in the deep retention state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.