Method for manufacturing logic device isolation in embedded storage process
US11670538B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 18, 2021 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Nov 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0411
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing logic device isolation in an embedded storage process, removing the pad silicon nitride and floating gate polysilicon layer in a shallow trench isolation area and retaining the floating gate oxide layer; depositing acid etching silicon nitride; removing the acid etching silicon nitride at the bottom of the shallow trench isolation and a portion of the silicon substrate adjacent to and under the shallow trench isolation, to form a trench and retain the acid etching silicon nitride on a side of the floating gate polysilicon layer close to the shallow trench isolation; remove the acid etching silicon nitride on the side of the floating gate polysilicon layer close to the shallow trench isolation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.