PCM metal shielding for wafer testing
US11670555B2 · kind B2 · utility
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5References
24Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 18, 2020 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Aug 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method and devices to reduce integrated circuit fabrication process yield loss due to undesired interactions between PCMs and the wafer test probes during wafer sorting tests are disclosed. The described methods entail the use of a properly patterned metal layer on the PCM dies adjacent to the product dies under test. Such patterned metal layers shield traces of the wafer probes from the circuits of the PCM dies. Various exemplary metal layer patterns are also presented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.