Power delivery for multi-chip-package using in-package voltage regulator
US11671010B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2020 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Feb 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a first substrate. A first die and a second die are disposed over the first substrate and are adjacent to one another. A plurality of first conductive bumps are disposed between the first substrate and the first die and between the first substrate and the second die. A second substrate is disposed below the first substrate. A plurality of second conductive bumps is disposed between the first substrate and the second substrate. An in-package voltage regulator (PVR) chip is disposed over the second substrate. A molding material is disposed over the first substrate and surrounds the first die, the second die, the plurality of first conductive bumps, the plurality of second conductive bumps, and the PVR chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.