Decoupling capacitor circuits
US11671084B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2021 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Aug 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a first metal-insulator-semiconductor capacitor, a second metal-insulator-semiconductor capacitor, and a metal-insulator-metal capacitor. A first terminal of the first metal-insulator-semiconductor capacitor is configured to receive a first reference voltage for a higher voltage domain, while a first terminal of the second metal-insulator-semiconductor capacitor is configured to receive a second reference voltage for the higher voltage domain. A second terminal of the first metal-insulator-semiconductor capacitor is conductively connected to a first terminal of the metal-insulator-metal capacitor, while a second terminal of the second metal-insulator-semiconductor capacitor is conductively connected to a second terminal of the metal-insulator-metal capacitor. The first terminal of the metal-insulator-metal capacitor is configured to receive a first supply voltage for a lower voltage domain, and the first terminal of the second metal-insulator-semiconductor capacitor is configured to receive a second supply voltage for the lower voltage domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.