Fast startup technique and circuit for a receiver
US11671092B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2021 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Sep 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various embodiments relate to a receiver, including: a first bias circuit configured to bias a first and second transistor based upon an bias enable signal and a receive enable signal; a first node between the first transistor and a third transistor; a second node between the second transistor and a fourth transistor; and a second bias circuit configured to bias the first node and the second node based upon the bias enable signal, wherein the third transistor is connected to a first differential output and the gate of the third transistor is connected to a first differential input, and wherein the fourth transistor is connected to a second differential output and the gate of the fourth transistor is connected to a second differential input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.