Handling interface clock rate mismatches between network devices
US11671281B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2021 |
| Grant date | Jun 6, 2023 |
| Priority date | — |
| Expiry date | Apr 6, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/16
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The performance of a switch or other network device is improved by adjusting the number of idle bytes transmitted between data units—that is, the size of the interpacket gap—to increase the bandwidth of a network interface. In some embodiments, the adjustments may be made in a manner designed to compensate for potential mismatches between the clock rate of the network interface and clock rates of interfaces of other network devices when retransmitting data received from those other network devices. In yet other embodiments, the adjustments may be designed to increase available bandwidth for other purposes. In an embodiment, the idle reduction logic is in a Media Access Control (“MAC”) layer of a network interface. The idle reduction logic may be enabled or disabled based on user preference, or programmatically based on factors such as a transmission utilization level for the MAC layer, buffer fill level, and so forth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.