Array substrate and method for manufacturing the same, display panel and display device
US11675237B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 27, 2021 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Apr 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate includes a base substrate, a light-shielding pattern, a buffer pattern, an active layer, a gate insulating layer and a first passivation layer provided with a first via, a second via and a third via, and a source and a drain. An entire orthographic projection of the active layer on the base substrate coincides with an orthographic projection of at least part of the buffer pattern on the base substrate. The orthographic projection of the buffer pattern on the base substrate is within a border of an orthographic projection of the light-shielding pattern on the base substrate, and its area is less than an area of the orthographic projection of the light-shielding pattern on the base substrate. One of the source and the drain is coupled to the active layer through the first via, and another one is coupled to the active layer through the second via and the light-shielding pattern through the third via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.