Computing device and series power supply method
US11675408B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2022 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Jan 10, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/0218
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device and a series power supply method are disclosed. The computing device includes: a hash board, including a series power supply circuit, which includes m layers of to-be-powered chips that are connected in series between a power supply positive electrode and a power supply negative electrode of the hash board, wherein highest-layer to-be-powered chips are connected to the power supply positive electrode, and bottommost-layer to-be-powered chips are connected to the power supply negative electrode, wherein the power supply positive electrode is configured to receive a higher potential relative to the power supply negative electrode; a control board, configured to provide, to the hash board, control signals and communication signals that are accessed to the series power supply circuit through a communication interface of the highest-layer to-be-powered chips and communicated to lower layers through the m layers of to-be-powered chips that are connected in series.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.