Patent · US Active

Memory-access control

US11675526B2 · kind B2 · utility

0Cited by

4References

21Claims

0Family size

Assignee

Nordic Semiconductor ASA · NO

Inventors

Hannu Talvitie · Oulu, FI
Marko Winblad · Trondheim, NO

Key dates

Filing date	Apr 17, 2019
Grant date	Jun 13, 2023
Priority date	—
Expiry date	Jun 3, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F21/79
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An electronic device comprises a processor, a memory, a memory controller for controlling access to the memory, a hardware security module, and a bus system, to which the processor, the memory controller, and the hardware security module are connected. The hardware security module uses its connection to the bus system to detect requests on the bus system that are sent by the processor. The hardware security module has a secure state and a non-secure state. When in the secure state, the hardware security module adds a secure-state signal to requests sent by the processor over the bus system. The memory controller determines whether memory-access requests include the secure-state signal, and denies access to a secure region of the memory in response to receiving memory-access requests that do not include the secure-state signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.