Process of programming field programmable gate arrays using partial reconfiguration
US11675604B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2019 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Nov 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Programming field programmable gate array (FPGA) digital electronic integrated circuits (ICs) or other ICs that support partial reconfiguration, a particular FPGA having reconfigurable partitions and primitive variations configurable in each of the reconfigurable partitions, comprises: before writing configuration bitstreams to the FPGA, compiling and storing primitive bitstreams for different primitive functions that can be implemented on the particular FPGA; receiving input in a graphical user interface to connect graphical blocks representing functional logic of an algorithm to implement on the particular FPGA, the graphical blocks relating to reconfigurable logic; automatically determining a subset of the primitive functions comprising particular primitive functions that correspond to the graphical blocks; obtaining, from the digital storage, a subset of the primitive bitstreams that corresponds to the subset of the primitive functions; using partial reconfiguration operations, writing the subset of the primitive bitstreams to the particular FPGA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.