Data protection system and method thereof for 3D semiconductor device
US11675731B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 30, 2020 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Apr 24, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0772
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data protection system and a data protection method for handling an errored command are provided. The data protection system includes a master device and a slave device. The master device is configured to send command. The slave device is coupled to the master device. The save device is configured to receive the command from the master device. The master device includes a master interface. The slave device includes a slave interface. The master interface and the slave interface are electrically connected via one or plurality of bonds and/or TSVs and configured for interfacing between the master device and the slave device. The errored command represents the command having a parity or other error. The slave device is further configured to receive the errored command and to respond the errored command according to read or write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.