Methods and systems for congestion prediction in logic synthesis using graph neural networks
US11675951B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2021 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Dec 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/09
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and system for assisting electronic chip design, comprising: receiving netlist data for a proposed electronic chip design, the netlist data including a list of circuit elements and a list of interconnections between the circuit elements; converting the netlist data to a graph that represents at least some of the circuit elements as nodes and represents the interconnections between the circuit elements as edges; extracting network embeddings for the nodes based on a graph topology represented by the edges; extracting degree features for the nodes based on the graph topology; and computing, using a graph neural network, a congestion prediction for the circuit elements that are represented as nodes based on the extracted network embeddings and the extracted degree features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.