Machine learning based layout nudging for design rule compliance
US11675960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2021 |
| Grant date | Jun 13, 2023 |
| Priority date | — |
| Expiry date | Nov 1, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a system and method for generating integrated circuit layouts are described herein. A computer implemented method for generating integrated circuit layouts includes receiving a first layout for an integrated circuit, segmenting the first layout into a plurality of different patches, each patch of the plurality of patches describing a discrete portion of the first layout, identifying a non-compliant patch of the plurality of patches, the non-compliant patch violating a design rule governing the manufacture of the integrated circuit, generating a transformation of the non-compliant patch using a machine learning model, and generating a second layout using the transformation and the first layout, where the second layout is compliant with the design rule.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.